1. Field of the Invention
The present invention relates to the field of digital communications, and in particular to a method and apparatus for encoding and decoding data.
2. Art Background
Advances in computer technology have increased the capability of information processing systems to transmit data at high rates. However, as system clock frequencies increase, the physical limitations introduced by system components become more pronounced and play a greater role in limiting achievable bandwidth. For example, as channel rates exceed 100 MHz, a significant portion of the data transfer cycle time may be occupied by jitter due to skew introduced by physical limitations inherent in system components.
FIGS. 1A and 1B illustrate the timing constraints of a typical synchronous transfer of data between a first (source) logic unit 1 and a second (destination) logic unit 2. The state of logic unit 1 is held in a register flip flop 3 having a data input D.sub.1, a clock input CK.sub.1 and a data output Q.sub.1. Similarly, the state of logic unit 2 is held in a register flip flop 4 having a data input D.sub.2, a clock input CK.sub.2 and a data output Q.sub.2. Both registers are clocked on the rising edge of pulses provided by a clock 5. Data is transferred between the two registers over a communication channel 6.
FIG. 1B illustrates the timing relationship between clock pulses arriving from clock 5 and data transferred over communication channel 6. The system hardware introduces a number of parameters that must be considered in order to execute a successful transfer of data. Each register has an inherent propagation delay t.sub.prop, which represents the time it takes for data introduced at the input of the register to appear at the output after the register has been clocked. Because of environmental factors and variations in silicon uniformity from register to register, the propagation delay ranges from a minimum value t.sub.propMIN to a maximum value t.sub.propMAX. The registers also require a set-up time t.sub.su, which represents the time that data must remain at the input of a register before it can be clocked. Once a register has been clocked, based on internal register delays, the data must remain at the register input for a hold time t.sub.h in order for the register to capture the data.
Taking into consideration these parameters, two equations must be satisfied in order for data to be transferred successfully from the input D.sub.1 of first register 3 to the output Q.sub.2 of second register 4: EQU t.sub.propMAX +t.sub.su &lt;T (1) EQU t.sub.propMIN &gt;t.sub.h, (2)
where T is the clock period.
The first equation indicates that the clock period T must be long enough to allow data to propagate through first register 3 and to sit at the input D.sub.2 of second register 4 before being clocked. The second equation requires that after the registers are clocked, the data appearing at the input D.sub.2 of the second register 4 will not change until after it has already sat at the input for at least time period t.sub.h.
These equations ignore the fact that the clock may not reach the registers at the same time because of various factors introducing delay into the system. The drivers at the source register and the receivers at the destination register of the communication channel are less than ideal and the respective environments of the driver and the receiver are not identical. For example, delay may be introduced by different wire lengths, different temperatures, ground shifts between the driver and receiver, ground bounce, and different power supply voltages. These environmental factors create a skew time t.sub.skew representing a difference in the arrival times of the clock pulse to the source register and to the destination register. The skew affects the above equations as follows: EQU t.sub.propMAX +t.sub.su +t.sub.skew &lt;T (1a) EQU t.sub.propMIN &gt;t.sub.h +t.sub.skew. (2a)
As shown by equation 1a, the environmental factors causing skew require that the clock period T be lengthened. As a consequence, skew slows the system data transfer rate, decreasing bandwidth.
One conventional method of minimizing skew entails transmitting the clock signal along the same communication channel as the data bits from source register to destination register. This eliminates many of the effects caused by environmental factors. However, this technique does not eliminate all forms of skew. For each clock edge, some data bits may be experiencing a transition from low to high voltage levels while others change from high to low. In other words, some data bits are changing in the same direction as the clock pulses while others are changing in the opposite direction. It is nearly impossible to achieve identical propagation delays through system components for both high-to-low and low-to-high signal transitions. Thus, when the clock and the data are making transitions in opposite directions, the different propagation delays experienced by the two pulses will introduce a new source of skew, thereby limiting the achievable bandwidth.
FIG. 2 illustrates the different propagation delays experienced by data making transitions in opposite directions. When data is clocked on the rising edge, this differential propagation delay effects the constraining equations in the following manner: EQU t.sub.propHLMAX +t.sub.su +t.sub.skew &lt;T (16) EQU t.sub.propLHMIN &gt;t.sub.h +t.sub.skew ( 26)
where t.sub.propLHMIN represents the minimum propagation delay experienced by a rising edge, and t.sub.propHLMAX the maximum propagation delay for a falling edge. In this example, it is assumed that t.sub.propHLMAX &gt;t.sub.propLHMIN, where t.sub.propLHMIN may be considered to be the minimum propagation delay t.sub.propMIN of an ideal system without the differential propagation delay caused by opposing clock/data transitions. Based on these equations, because t.sub.propHLMAX &gt;t.sub.propMAX, the clock period T must be increased further in order to validate the data, resulting in a further decrease in the system bandwidth.
FIGS. 3A and 3B illustrate the timing constraints of a more sophisticated data transfer system that, in addition to transmitting the clock along with the data signals, uses both clock edges to validate the data captured at the destination. This system has the added advantage of signalling at a lower frequency to reach higher data rates than the system of FIG. 1A.
All data bits change coincident with the input Clock A signal. In this embodiment, on the rising edge of the clock the odd data bits are captured at the destination logic unit 2 by data register 10. On the falling edge of the clock, the even data bits are captured at the destination by data register 11. The delay at the destination before the clock inputs is sufficiently long to meet the set up and hold time requirements of both registers 10 and 11. This insures that the data is valid at the data inputs of those registers.
The waveform of FIG. 3B illustrates the timing relationship at the destination logic unit 2. For the data to be captured reliably at the destination, the bit cell time T must be large enough to allow for the uncertainty in the arrival time of the clock edge caused by the skew between the falling and rising edges of the data and clock. In most systems, it is not known whether the rising edge will occur before the falling edge or vice versa. Typically the only known parameter is the skew or uncertainty in arrival times between any two signals. The skew causes a "window of uncertainty" in the data bits and clock received at the destination 2. This window is labeled "invalid" in FIG. 3B. The window of uncertainty also causes the generation time of Clock B to also be uncertain, creating "interval X". To guarantee that the setup and hold times of registers 10 and 11 are met, the valid data time must be the sum of the setup time, the hold time and interval X. This tends to elongate the bit cell time T, thereby reducing the data transfer rate. The bit cell time T=setup time+hold time+interval X+invalid time, resulting in a limitation of the transfer frequency to EQU F=1/2(setup time+hold time+interval X+invalid time)
In some systems, interval X and the invalid time are approximately equal, so that F can be simplified to EQU F=1/[2(setup time+hold time)+4(interval X)]
This equation indicates that as the devices become faster and the setup and hold times decrease, the skew between the rising and falling edges (interval X) will dominate the equation and ultimately result in substantial limitations of system performance.